Difference between conditional operator & if .. else

Hi all,

Consider the following verilog code

module if_cond ;
reg [1:0] a,b ;
reg [1:0] c2 ;
wire [1:0] c1 ;
reg [1:0] foo ;

assign c1 = foo ? a : b ;

always @ ( foo or a or b )
begin
if ( foo )
c2 = a ;
else
c2 = b ;
end

endmodule

What is the difference between the variables C1 & C2 ? Is there any ?

Learn to display color messages using Verilog

Hi all,

How many among you know that you can actually display color messages using Verilog ?

Using the following piece of code, one can actually display color messages ( possible on for Linux & Unix terminals )

module colour();

initial
begin
$write("%c[1;34m",27);
$display("*********** This is in blue ***********");
$write("%c[0m",27);

$display("%c[1;31m",27);
$display("*********** This is in red ***********");
$display("%c[0m",27);

$display("%c[4;33m",27);
$display("*********** This is in brown ***********");
$display("%c[0m",27);

$display("%c[5;34m",27);
$display("*********** This is in green ***********");
$display("%c[0m",27);

$display("%c[7;34m",27);
$display("*********** This is in Back groung colour ***********");
$display("%c[0m",27);


end
endmodule



Code developed by Gopi

How many times does the "for" loop gets executed

Hi all,

How many times does the for loop gets executed in the following verilog code

reg [3:0] loop ;

for ( loop = 0 ; loop <= 15 ; loop = loop + 1 )
begin
$display("Inside the loop for the %d time",loop);
end

Design a XOR gate using the following custom gates

This particular one was given in an interview at IBM over 10 years ago.

Due to the war in the land of Logicia there is a shortage of XOR gates. Unfortunately, the only logic gates available are two weird components called “X” and “Y”. The truth table of both components is presented below - Z represents a High-Z value on the output.
Could you help the poor engineers of Logicia to build an XOR gate?

Model a buffer of 20 units in verilog

HI all, Which is the correct way of modeling a buffer of 20 units in verilog

Option 1 : #20 a = b ;
Option 2 : a = #20 b ;
Option 3 : #20 a <= b ;
Option 4 : a <= #20 b ;

Difference between these two verilog statements

Hi all, Can you find the difference between these two verilog (VERILOG-1995) statements

$fopen("filename");
$fopen("filename","w");

There is more than one difference ....

Interview Questions

* Define setup window and hold window ?
* What is the effect of clock skew on setup and hold ?
* In a multicycle path, where do we analyze setup and where do we analyze hold ?
* How many test clock domains are there in a chip ?
* How enables of clock gating cells are taken care at the time of scan ?
* Difference between functional coverage and code coverage ?
* Does 100% code coverage means 100% functional coverage & vice versa?
* What do you mean by useful skew ?
* What is shift miss and capture miss in transition delay faults ?
* What is the structure of clock gating cell ?
* How can you say that placing clock gating cells at synthesis level will reduce the area of the design ?
* How will you decide to insert the clock gating cell on logic where data enable is going for n number of flops
* What is the concept of synchronizers ?
* What are lockup latches?
* What is the concept of power islands ?
* What does OCV, Derate and CRPR mean in STA ?
* What is dynamic power estimation ?
* On AHB bus which path would you consider for worst timing ?
* What is the difference between blocking & non-blocking statements in verilog ?
* What are the timing equations for setup and hold, with & without considering timing skew ?
* Design a XOR gate with 2-input NAND gates
* Design AND gate with 2X1 MUX
* Design OR gate with 2X1 MUX
* Design T-Flip Flop using D-Flip Flop
* In a synchronizer how you can ensure that the second stage flop is getting stabilized input?
* Design a pulse synchronizer
* Calculate the depth of a buffer whose clock ratio is 4:1 (wr clock is fatser than read clock)
* Design a circuit that detects the negedge of a signal. The output of this circuit should get deasserted along with the input signal
* Design a DECODER using DEMUX
* Design a FSM for 10110 pattern recognition
* 80 writes in 100 clock cycles, 8 reads in 10 clock cycles. What is the minimum depth of FIFO?
* Why APB instead of AHB ?
* case, casex, casez if synthesized what would be the hardware
* Define monitor functions for AHB protocol checker
* What is the use of AHB split, give any application
* Can we synchronize data signals instead of control signals ?