Rules for govering usage of a verilog Function

The following rules govern the usage of a Verilog function construct:

• A function cannot advance simulation-time, using constructs like #, @.etc.
• A function shall not have nonblocking assignments.
• A function without a range defaults to a one bit reg for the return value.
• It is illegal to declare another object with the same name as the function in the scope where the function is declared