Introduction to Metastability

Any asynchronous input from the outside world to a clocked circuit represents
a source of unreliability, since there is always some residual probability
that the clocked circuit will sample the asynchronous signal just at the
time that it is changing.

From a specification point of view, synchronous elements such as flip flops
specify a Setup time and a Hold time. By its nature an
asynchronous input cannot be reliably expected to meet this specification, and
so it will have transitions that fall within the timing window that is bounded
by these two specifications. When this occurs, the result can be one of three
scenarios:

1) The state of the signal prior to the transition is used.
2) The state of the signal after the transition is used.
3) The flip flop goes metastable.

The first two possibilities are of no consequence, since the signal is
asynchronous, but the third possibility is what the rest of this article is
about.

Metastability caused havoc in synchronous systems. It is caused by the unstable
equilibrium state for example when a pair of cross coupled CMOS inverters are
stuck at mid-voltages. It is impossible to determine how long such a state
persists. Unfortunately, due to the complexities in today's systems, it is not
possible for the designer to avoid this type of situation.

The most common approach to minimizing the problems of metastability propagating
into our synchronous systems is to use a synchronizing circuit to take the
asynchronous input signal, and align it to the timing regimen of the rest of the
system.

The synchronizer though can go metastable itself, and the goal of a designer is
to minimize the probability of this occuring and propagating to the output of
the synchronizer. In current (2004) technology, this can usually be achieved
with a two stage or three stage synchronizer.