Tuesday, July 29, 2008

How many times does the "for" loop gets executed

Hi all,

How many times does the for loop gets executed in the following verilog code

reg [3:0] loop ;

for ( loop = 0 ; loop <= 15 ; loop = loop + 1 )
$display("Inside the loop for the %d time",loop);

Design a XOR gate using the following custom gates

This particular one was given in an interview at IBM over 10 years ago.

Due to the war in the land of Logicia there is a shortage of XOR gates. Unfortunately, the only logic gates available are two weird components called “X” and “Y”. The truth table of both components is presented below - Z represents a High-Z value on the output.
Could you help the poor engineers of Logicia to build an XOR gate?

Model a buffer of 20 units in verilog

HI all, Which is the correct way of modeling a buffer of 20 units in verilog

Option 1 : #20 a = b ;
Option 2 : a = #20 b ;
Option 3 : #20 a <= b ;
Option 4 : a <= #20 b ;

Difference between these two verilog statements

Hi all, Can you find the difference between these two verilog (VERILOG-1995) statements


There is more than one difference ....

Monday, July 28, 2008

Interview Questions

* Define setup window and hold window ?
* What is the effect of clock skew on setup and hold ?
* In a multicycle path, where do we analyze setup and where do we analyze hold ?
* How many test clock domains are there in a chip ?
* How enables of clock gating cells are taken care at the time of scan ?
* Difference between functional coverage and code coverage ?
* Does 100% code coverage means 100% functional coverage & vice versa?
* What do you mean by useful skew ?
* What is shift miss and capture miss in transition delay faults ?
* What is the structure of clock gating cell ?
* How can you say that placing clock gating cells at synthesis level will reduce the area of the design ?
* How will you decide to insert the clock gating cell on logic where data enable is going for n number of flops
* What is the concept of synchronizers ?
* What are lockup latches?
* What is the concept of power islands ?
* What does OCV, Derate and CRPR mean in STA ?
* What is dynamic power estimation ?
* On AHB bus which path would you consider for worst timing ?
* What is the difference between blocking & non-blocking statements in verilog ?
* What are the timing equations for setup and hold, with & without considering timing skew ?
* Design a XOR gate with 2-input NAND gates
* Design AND gate with 2X1 MUX
* Design OR gate with 2X1 MUX
* Design T-Flip Flop using D-Flip Flop
* In a synchronizer how you can ensure that the second stage flop is getting stabilized input?
* Design a pulse synchronizer
* Calculate the depth of a buffer whose clock ratio is 4:1 (wr clock is fatser than read clock)
* Design a circuit that detects the negedge of a signal. The output of this circuit should get deasserted along with the input signal
* Design a DECODER using DEMUX
* Design a FSM for 10110 pattern recognition
* 80 writes in 100 clock cycles, 8 reads in 10 clock cycles. What is the minimum depth of FIFO?
* Why APB instead of AHB ?
* case, casex, casez if synthesized what would be the hardware
* Define monitor functions for AHB protocol checker
* What is the use of AHB split, give any application
* Can we synchronize data signals instead of control signals ?

Verilog Questions

# What is the difference between $display and $monitor and $write and $strobe?
# What is the difference between code-compiled simulator and normal simulator?
# What is the difference between wire and reg?
# What is the difference between blocking and non-blocking assignments?
# What is the significance Timescale directivbe?
# What is the difference between bit wise, unary and logical operators?
# What is the difference between task and function?
# What is the difference between casex, casez and case statements?
# Which one preferred-casex or casez?
# For what is defparam used?
# What is the difference between "= =" and "= = =" ?
# What is a compiler directive like 'include' and 'ifdef'?
# Write a verilog code to swap contents of two registers with and without a temporary register?
# What is the difference between inter statement and intra statement delay?
# What is delta simulation time?
# What is difference between Verilog full case and parallel case?
# What you mean by inferring latches?
# How to avoid latches in your design?
# Why latches are not preferred in synthesized design?
# How blocking and non blocking statements get executed?
# Which will be updated first: is it variable or signal?
# What is sensitivity list?
# If you miss sensitivity list what happens?
# In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?
# In a pure sequential circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?
# What is general structure of Verilog code you follow?
# What are the difference between Verilog and VHDL?
# What are system tasks?
# List some of system tasks and what are their purposes?
# What are the enhancements in Verilog 2001?
# Write a Verilog code for synchronous and asynchronous reset?
# What is pli? why is it used?
# What is file I/O?
# What is difference between freeze deposit and force?
# Will case always infer priority register? If yes how? Give an example.
# What are inertial and transport delays ?
# What does `timescale 1 ns/ 1 ps' signify in a verilog code?
# How to generate sine wav using verilog coding style?
# How do you implement the bi-directional ports in Verilog HDL?
# How to write FSM is verilog?
# What is verilog case (1)?
# What are Different types of Verilog simulators available?
# What is Constrained-Random Verification ?
# How can you model a SRAM at RTL Level?
# What are different types of timing verifications?
# What is the difference between Formal verification and Logic verification?
# What is the difference between verification and validation? And what are procedures of doing the same?
# What is the difference between testing and verification?

Friday, July 25, 2008

Try to find the corner case in this verilog code

Hi Everyone, The following is a small verilog code which below models a flip-flop with asynchronous set/reset logic (active low). The model synthesizes correctly, but there is a corner case where simulation results are incorrect. What is the corner case?

always_ff @( posedge clk
or negedge rst_n // active-low reset
or negedge set_n // active-low set
if (!rst_n) // reset has priority over set
q_out <= '0; // reset all bits to zero
else if (!set_n)
q_out <= '1; // set all bits to one
q_out <= data_in; // d input assignment

Hope this question will tickle the technical senses of all the ASIC verification engineers