Tuesday, September 16, 2008

Verilog Questions

Q: What is the difference between a Verilog task and a Verilog function?


The following rules distinguish tasks from functions:

1. A function shall execute in one simulation time unit

A task can contain time-controlling statements.

2. A function cannot enable a task

A task can enable other tasks or functions.

3. A function shall have at least one input type argument and shall not have an output or inout type argument;

A task can have zero or more arguments of any type.

4. A function shall return a single value;

A task shall not return a value.

Q: Given the following Verilog code, what value of "a" is displayed?

always @(clk) begin

a = 0;

a <= 1;




This is a tricky one! Verilog scheduling semantics basically imply a four-level deep queue for the current simulation time:

1: Active Events (blocking statements)

2: Inactive Events (#0 delays, etc)

3: Non-Blocking Assign Updates (non-blocking statements)

4: Monitor Events ($display, $monitor, etc).

Since the "a = 0" is an active event, it is scheduled into the 1st "queue". The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue. Finally, the display statement is placed into the 4th queue. Only events in the active queue are completed this sim cycle, so the "a = 0" happens, and then the display shows a = 0. If we were to look at the value of a in the next sim cycle, it would show 1.

Q: Given the following snippet of Verilog code, draw out the waveforms for clk and a

always @(clk) begin

a = 0;

#5 a = 1;



10 30 50 70 90 110 130

___ ___ ___ ___ ___ ___ ___

clk ___| |___| |___| |___| |___| |___| |___| |___

a ___________________________________________________________

This obviously is not what we wanted, so to get closer, you could use "always @ (posedge clk)" instead, and you'd get

10 30 50 70 90 110 130

___ ___ ___ ___ ___ ___ ___

clk ___| |___| |___| |___| |___| |___| |___| |___

___ ___

a _______________________| |___________________| |_______

Q: What is the difference between the following two lines of Verilog code?

#5 a = b;

a = #5 b;


#5 a = b; Wait five time units before doing the action for "a = b;".

The value assigned to a will be the value of b 5 time units hence.

a = #5 b; The value of b is calculated and stored in an internal temp register.

After five time units, assign this stored value to a.

Q: What is the difference between:

c = foo ? a : b; and

if (foo) c = a;

else c = b;


The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b = 'b11, you'd get c = 'b1x.

On the other hand, if treats Xs or Zs as FALSE, so you'd always get c = b.

Q: Using the given, draw the waveforms for the following versions of a (each version is separate, i.e. not in the same run):

reg clk;

reg a;

always #10 clk = ~clk;

(1) always @(clk) a = #5 clk;

(2) always @(clk) a = #10 clk;

(3) always @(clk) a = #15 clk;

Now, change a to wire, and draw for:

(4) assign #5 a = clk;

(5) assign #10 a = clk;

(6) assign #15 a = clk;


10 30 50 70 90 110 130

___ ___ ___ ___ ___ ___ ___

clk ___| |___| |___| |___| |___| |___| |___| |___

___ ___ ___ ___ ___ ___ ___

(1)a ____| |___| |___| |___| |___| |___| |___| |_

___ ___ ___ ___ ___ ___ ___

(2)a ______| |___| |___| |___| |___| |___| |___|

(3)a __________________________________________________________

Since the #delay cancels future events when it activates, any delay over the actual 1/2 period time of the clk flatlines...

With changing a to a wire and using assign, we just accomplish the same thing...

10 30 50 70 90 110 130

___ ___ ___ ___ ___ ___ ___

clk ___| |___| |___| |___| |___| |___| |___| |___

___ ___ ___ ___ ___ ___ ___

(4)a ____| |___| |___| |___| |___| |___| |___| |_

___ ___ ___ ___ ___ ___ ___

(5)a ______| |___| |___| |___| |___| |___| |___|

(6)a __________________________________________________________

Friday, September 5, 2008

Rules for govering usage of a verilog Function

The following rules govern the usage of a Verilog function construct:
  • A function cannot advance simulation-time, using constructs like #, @.etc.
  • A function shall not have nonblocking assignments.
  • A function without a range defaults to a one bit reg for the return value.
  • It is illegal to declare another object with the same name as the function in the scope where the function is declared

Synthesis Questions

  • What are the various Design constraints used while performing Synthesis for a design?
    Ans: 1. Create the clocks (frequency, duty-cycle).
    2. Define the transition-time requirements for the input-ports
    3. Specify the load values for the output ports
    4. For the inputs and the output specify the delay values(input delay and ouput delay), which are already consumed by the neighbour chip.
    5. Specify the case-setting (in case of a mux) to report the timing to a specific paths.
    6. Specify the false-paths in the design
    7. Specify the multi-cycle paths in the design.
    8. Specify the clock-uncertainity values(w.r.t jitter and the margin values for setup/hold).
    19. Specify few verilog constructs which are not supported by the synthesis tool.

  • What are the various design changes you do to meet design power targets?
    Ans: Design with Multi-VDD designs, Areas which requires high performance, goes with high VDD and areas which needs low-performance are working with low Vdd's, by creating Voltage-islands and making sure that appropriate level-shifters are placed in the cross-voltage domains Designing with Multi-Vt's(threshold voltages), areas which require high performance, goes with low Vt, but takes lot of leakage current, and areas which require low performance with high Vt cells, which has low leakage numbers, by incorporating this design process, we can reduce the leakage power. As in the design , clocks consume more amount of power, placing optimal clock-gating cells, in the design and controlling them by the module enable's gives a lot of power-savings.
    As clock-tree's always switch making sure that most number of clock-buffers are after the clock-gating cells, this reduces the switching there by power-reduction.
    Incorporating Dynamic Voltage and Frequency scaling (DVFS) concepts based on the application , there by reducing the systems voltage and frequency numbers when the application does not require to meet the performance targets. Ensure the design with IR-Drop analysis and ground-bounce analysis, is with-in the design specification requirement. Place power-switches, so that the leakage power can be reduced. related information.

  • what is meant by Library Characterizing
    Ans: Characterization in terms of delay, power consumption,..

  • what is meant by wireload model
    Ans: In the synthesis tool, in order to model the wires we use a concept called as "Wireload models", Now the question is what is wireload models: Wireload models are statistical based on models with respect to fanout. say for a particular technology based on our previous chip experience we have a rough estimate we know if a wire goes for "n" number of fanin then we estimate its delay as say "x" delay units. So a model file is created with the fanout numbers and corresponding estimated delay values. This file is used while performing Synthesis to estimate the delay for Wires, and to estimate the delay for cells, technology specific library model files will be available

  • what are the measures to be taken to design for optimized area
    Ans: As silicon real-estate is very costly and saving is directly propotional to the company's revenue generation lot of emphasize is to design which has optimial utilization in the area-front. The steps to reduce area are
    If the path is not timing-critical, then optimize the cells to use the low-drive strength cells so that there will saving in the area. Abut the VDD rows Analyzing the utilization numbers with multiple floor-planning versions which brings up with optimized area targets.

  • what all will you be thinking while performing floorplan
    Ans: Study the data-flow graph of the design and place the blocks accordingly, to reducing the weighted sum of area, wire-length. Minimize the usuage of blocks other-than square shapes, having notches Place the blocks based on accessibility/connectivity, thereby reducing wire-length. Abut the memory, if the pins are one-sided, there-by area could be reduced. If the memory communicates to the outside world more frequently , then placing at the boundary makes much of a sense. Study the number of pins to be routed, with the minimum metal width allowed , estimate the routability issues. Study the architecture and application , so that the blocks which will be enabled should be scattered, to reduce the power-ground noise.

  • what are the measures in the Design taken for Meeting Signal-integrity targets
    Ans: As more and more devices are getting packed, results in more congested areas, and coupling capactiances dominating the wire-capacitance, creates SI violations. Let's see now by what are all the measures we can reduce/solve it.
    As clock-tree runs across the whole chip, optimizing the design for SI, is essential route the clock with double-pitch and triple spacing. In-case of SI violation, spacing the signal nets reduces cross-talk impacts.
    Shield the nets with power-nets for high frequency signal nets to prevent from SI.
    Enable SI aware routing , so that the tool takes care for SI
    Ensure SI enabled STA runs, and guarantee the design meeting the SI requirements
    Route signals on different layers orthogonal to each other
    Minimize the parallel run-length wires, by inserting buffers.

VLSI Concepts questions

  1. Explain why & how a MOSFET works
  2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation
  3. Explain the various MOSFET Capacitances & their significance
  4. Draw a CMOS Inverter. Explain its transfer characteristics
  5. Explain sizing of the inverter
  6. How do you size NMOS and PMOS transistors to increase the threshold voltage?
  7. What is Noise Margin? Explain the procedure to determine Noise Margin
  8. Give the expression for CMOS switching power dissipation
  9. What is Body Effect?
  10. Describe the various effects of scaling
  11. Give the expression for calculating Delay in CMOS circuit
  12. What happens to delay if you increase load capacitance?
  13. What happens to delay if we include a resistance at the output of a CMOS circuit?
  14. What are the limitations in increasing the power supply to reduce delay?
  15. How does Resistance of the metal lines vary with increasing thickness and increasing length?
  16. You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
  17. What happens if we increase the number of contacts or via from one metal layer to the next?
  18. Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
  19. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
  20. Draw the stick diagram of a NOR gate. Optimize it
  21. For CMOS logic, give the various techniques you know to minimize power consumption
  22. What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
  23. Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
  24. In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
  25. Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
  26. Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
  27. Why don't we use just one NMOS or PMOS transistor as a transmission gate?
  28. For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
  29. Draw a 6-T SRAM Cell and explain the Read and Write operations
  30. Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
  31. What happens if we use an Inverter instead of the Differential Sense Amplifier?
  32. Draw the SRAM Write Circuitry
  33. Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?
  34. How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
  35. What's the critical path in a SRAM?
  36. Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?
  37. Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers
  38. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
  39. How can you model a SRAM at RTL Level?
  40. What�s the difference between Testing & Verification?
  41. For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
  42. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

Digital Design questions

  1. Give two ways of converting a two input NAND gate to an inverter
  2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any sequential ckt)
  3. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
  4. Give a circuit to divide frequency of clock cycle by two
  5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
  6. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can't resize the combinational circuit transistors)
  7. The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this?
  8. What are the different Adder circuits you studied?
  9. Give the truth table for a Half Adder. Give a gate level implementation of the same.
  10. Draw a Transmission Gate-based D-Latch.
  11. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
  12. How do you detect if two 8-bit signals are same?
  13. How do you detect a sequence of "1101" arriving serially from a signal line?

VLSI Interview Questions

what are the differences between SIMULATION and SYNTHESIS

Simulation <= verify your design.
synthesis <= Check for your timing
Simulation is used to verify the functionality of the circuit.. a)Functional Simulation:study of ckt's operation independent of timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met.
Synthesis:One of the foremost in back end steps where by synthesizing is nothing but converting VHDL or VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology.Basically the synthesis tools convert the design description into equations or components

Can u tell me the differences between latches & flipflops?

There are 2 types of circuits:
1. Combinational
2. Sequential

Latches and flipflops both come under the category of "sequential circuits", whose output depends not only on the current inputs, but also on previous inputs and outputs.

Difference: Latches are level-sensitive, whereas, FF are edge sensitive. By edge sensitive, I mean O/p changes only when there is a clock transition.( from 1 to 0, or from 0 to 1)

Example: In a flipflop, inputs have arrived on the input lines at time= 2 seconds. But, output won't change immediately. At time = 3 seconds, clock transition takes place. After that, O/P will change.
Flip-flops are of 2 types:
1.Positive edge triggered
2. negative edge triggered

1)fllipflops take twice the nymber of gates as latches
2) so automatically delay is more for flipflops
3)power consumption is also more

latch does not have a clock signal, whereas a flip-flop always does.

What is slack?

The slack is the time delay difference from the expected delay(1/clock) to the actual delay in a particular path.
Slack may be +ve or -ve.

Equivalence between VHDL and C?

There is concept of understanding in C there is structure.Based upon requirement structure provide facility to store collection of different data types.

In VHDL we have direct access to memory so instead of using pointer in C (and member of structure) we can write interface store data in memory and access it.

RTL and Behavioral

Register transfer language means there should be data flow between two registers and logic is in between them for end registers data should flow.

Behavioral means how hardware behave determine the exact way it works we write using HDL syntax.For complex projects it is better mixed approach or more behavioral is used.