* Define setup window and hold window ?
* What is the effect of clock skew on setup and hold ?
* In a multicycle path, where do we analyze setup and where do we analyze hold ?
* How many test clock domains are there in a chip ?
* How enables of clock gating cells are taken care at the time of scan ?
* Difference between functional coverage and code coverage ?
* Does 100% code coverage means 100% functional coverage & vice versa?
* What do you mean by useful skew ?
* What is shift miss and capture miss in transition delay faults ?
* What is the structure of clock gating cell ?
* How can you say that placing clock gating cells at synthesis level will reduce the area of the design ?
* How will you decide to insert the clock gating cell on logic where data enable is going for n number of flops
* What is the concept of synchronizers ?
* What are lockup latches?
* What is the concept of power islands ?
* What does OCV, Derate and CRPR mean in STA ?
* What is dynamic power estimation ?
* On AHB bus which path would you consider for worst timing ?
* What is the difference between blocking & non-blocking statements in verilog ?
* What are the timing equations for setup and hold, with & without considering timing skew ?
* Design a XOR gate with 2-input NAND gates
* Design AND gate with 2X1 MUX
* Design OR gate with 2X1 MUX
* Design T-Flip Flop using D-Flip Flop
* In a synchronizer how you can ensure that the second stage flop is getting stabilized input?
* Design a pulse synchronizer
* Calculate the depth of a buffer whose clock ratio is 4:1 (wr clock is fatser than read clock)
* Design a circuit that detects the negedge of a signal. The output of this circuit should get deasserted along with the input signal
* Design a DECODER using DEMUX
* Design a FSM for 10110 pattern recognition
* 80 writes in 100 clock cycles, 8 reads in 10 clock cycles. What is the minimum depth of FIFO?
* Why APB instead of AHB ?
* case, casex, casez if synthesized what would be the hardware
* Define monitor functions for AHB protocol checker
* What is the use of AHB split, give any application
* Can we synchronize data signals instead of control signals ?