Thursday, March 10, 2011

Difference between Initial block and Final block in SV

Final block is a new concept which was introduced in System Verilog.

The basic difference between these two are evident from the nomenclature, i.e, Initial block starts getting executed during simulation time t=0 while the Final block gets executed when the simulation is completed.

Before getting into details, there is one similarity between these two sequential block of codes, both of them gets executed only once during the simulation

Now getting back to the difference between Initial and Final blocks, Initial blocks can contain some # delays or wait statements or some wait for events, but the Final block should not contains any such things.

Final block should get executed with 0 simulation time. Ideally this is used for test case status reporting or some display statements that have to be printed after the test case execution is completed

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Unknown said...

In the first statement you said that final block will be executed at the end of simulation...
but in the last statement you are saying it should be executed at 0 simulation time!how come??

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