Verilog Questions

# What is the difference between $display and $monitor and $write and $strobe?
# What is the difference between code-compiled simulator and normal simulator?
# What is the difference between wire and reg?
# What is the difference between blocking and non-blocking assignments?
# What is the significance Timescale directivbe?
# What is the difference between bit wise, unary and logical operators?
# What is the difference between task and function?
# What is the difference between casex, casez and case statements?
# Which one preferred-casex or casez?
# For what is defparam used?
# What is the difference between "= =" and "= = =" ?
# What is a compiler directive like 'include' and 'ifdef'?
# Write a verilog code to swap contents of two registers with and without a temporary register?
# What is the difference between inter statement and intra statement delay?
# What is delta simulation time?
# What is difference between Verilog full case and parallel case?
# What you mean by inferring latches?
# How to avoid latches in your design?
# Why latches are not preferred in synthesized design?
# How blocking and non blocking statements get executed?
# Which will be updated first: is it variable or signal?
# What is sensitivity list?
# If you miss sensitivity list what happens?
# In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?
# In a pure sequential circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?
# What is general structure of Verilog code you follow?
# What are the difference between Verilog and VHDL?
# What are system tasks?
# List some of system tasks and what are their purposes?
# What are the enhancements in Verilog 2001?
# Write a Verilog code for synchronous and asynchronous reset?
# What is pli? why is it used?
# What is file I/O?
# What is difference between freeze deposit and force?
# Will case always infer priority register? If yes how? Give an example.
# What are inertial and transport delays ?
# What does `timescale 1 ns/ 1 ps' signify in a verilog code?
# How to generate sine wav using verilog coding style?
# How do you implement the bi-directional ports in Verilog HDL?
# How to write FSM is verilog?
# What is verilog case (1)?
# What are Different types of Verilog simulators available?
# What is Constrained-Random Verification ?
# How can you model a SRAM at RTL Level?
# What are different types of timing verifications?
# What is the difference between Formal verification and Logic verification?
# What is the difference between verification and validation? And what are procedures of doing the same?
# What is the difference between testing and verification?

Try to find the corner case in this verilog code

Hi Everyone, The following is a small verilog code which below models a flip-flop with asynchronous set/reset logic (active low). The model synthesizes correctly, but there is a corner case where simulation results are incorrect. What is the corner case?


always_ff @( posedge clk
or negedge rst_n // active-low reset
or negedge set_n // active-low set
)
if (!rst_n) // reset has priority over set
q_out <= '0; // reset all bits to zero
else if (!set_n)
q_out <= '1; // set all bits to one
else
q_out <= data_in; // d input assignment

Hope this question will tickle the technical senses of all the ASIC verification engineers