Hi all,
Check the code below
module test;
reg clk,clk1,q,q1,d;
initial
begin
clk = 1'b0;
clk1 = 1'b0;
d = 1'b0;
#15 d <= 1'b1;
end
always
#5 clk = ~clk;
always
#5 clk1 <= ~clk1;
always @(posedge clk)
begin
q<=d;
end
always @(posedge clk1)
begin
q1<=d;
end
initial
begin
$monitor($realtime,"\t clk = %b, clk1 = %b, q = %b, q1 = %b, d = %b ",clk,clk1,q,q1,d);
#100 $finish;
end
endmodule
What is the output of the code above, justify it
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