This post tries to explains the basic differences between Static Timing Analysis ( STA ) and Gate-Level Simulations ( Dynamic Timing Analysis )
Dynamic Timing Analysis :
- The design is simulated in full timing mode.
- Not all possibilities tested as it is dependent on the input test vectors.
- Simulations in full timing mode are slow and require a lot of memory.
- Best method to check asynchronous interfaces or interfaces between different timing domains.
- Requires huge amount of computing resources (CPU time, disk space for the waveforms, etc.).
- Helps to validate the constraints mentioned during synthesis like false paths, multi-cycle paths, etc.
- Helps validate your formal verification like set_comparison and set_equivalent constraints etc
- Reset sequences are also more problematic in gate-level simulations, so this is a common place to catch them. Synchronous reset issues that cause unknowns to pass into the flops when the reset is synthesized as part of the logic can be caught explicitly in gate-level simulation.
- Validation of cross-clock domain false/multicycle paths, user defined modes of operation with case_analysis and clock phase relationships can be error-prone.
- Helps to validate the most critical power up sequences in the design
Static timing Analysis :
- The delays over all paths are added up.
- All possibilities, including false paths, verified without the need for test vectors.
- Much faster than simulations, hours as opposed to days.
- Not good with asynchronous interfaces or interfaces between different timing domains.
Static verification methodologies such as static timing analysis and formal verification are required to meet aggressive schedules, since they reduce the need to run full back annotated regression. However, it must be understood that the static verification environments are constraint based. Therefore, the analysis is only as accurate as the constraints that drive it.
With respect to static vs. dynamic timing verification, I think it is of primary importance that all asynchronous interfaces are thoroughly stressed in back annotated simulations. In most multi-clock domain designs, many or all of the clocks are treated as false paths in static timing analysis. I think back annotated simulations are the most dependable method of verifying the correct implementation of synchronizers and FIFO's at asynchronous boundaries, and consider back annotated simulations a necessary sign-off step before tapeout.