Hi all,
Consider the following verilog code
module if_cond ;
reg [1:0] a,b ;
reg [1:0] c2 ;
wire [1:0] c1 ;
reg [1:0] foo ;
assign c1 = foo ? a : b ;
always @ ( foo or a or b )
begin
if ( foo )
c2 = a ;
else
c2 = b ;
end
endmodule
What is the difference between the variables C1 & C2 ? Is there any ?
1 comment:
Say foo is 2'b1x a=2'b00 b=2'b11:
Take the first example, it merges the false expression b with foo that is c becomes 2'b1x where as the if else statement always results in c=b!! So better to use if else..
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